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1 ltc1555/ltc1556 sim power supply and level translator features step-up/step-down charge pump generates 5v input voltage range: 2.7v to 10v output current: 10ma (v in 2.7v) 20ma (v in 3v) 3v to 5v signal level translators > 10kv esd on all sim contact pins short-circuit and overtemperature protected very low operating current: 60 a very low shutdown current: < 1 a soft start limits inrush current at turn-on programmable 3v or 5v output voltage 650khz switching frequency auxiliary 4.3v ldo/power switch (ltc1556 only) available in a 16- and 20-pin narrow ssop descriptio n u the ltc 1555/ltc1556 provide power conversion and level shifting needed for 3v gsm cellular telephones tointerface with either 3v or 5v subscriber identity mod- ules (sims). these parts contain a charge pump dc/dc converter that delivers a regulated 5v to the sim card. input voltage may range from 2.7v to 10v, allowing direct connection to the battery. output voltage may be programmed to 3v, 5v or direct connection to the v in pin. a soft start feature limits inrush current at turn-on,mitigating start-up problems that may result when the input is supplied by another low power dc/dc converter. the ltc1556 also includes an auxiliary ldo regulator/ power switch that may be used to power the frequency synthesizer or other low power circuitry. battery life is maximized by 60 a operating current and 1 a shutdown current. board area is minimized by minia- ture 16- and 20-pin narrow ssop packages and the needfor only three small external capacitors. typical applicatio n u gsm cellular telephone sim interface 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 cin rin data ddrv dv cc ss m1 m0 clk rst i/o v cc 5v 5% i vcc 10ma gnd clk rst i/o v cc v in c1 + c1 gnd 0.1 f 10 f ltc1555 3v gsm controller sim v in 2.7v to 10v 3v 10 f 1555/56 ta01 v cc + , ltc and lt are registered trademarks of linear technology corporation. sim interface in gsm cellular telephones smart card readers applicatio n s u downloaded from: http:///
2 ltc1555/ltc1556 parameter conditions min typ max units v in operating voltage 2.7 10 v dv cc operating voltage 1.8 5.5 v v in operating current 2.7v v in 5v, v cc = 5v, i vcc = 0 60 100 a 5v < v in 10v, v cc = 5v, i vcc = 0 75 135 a v in shutdown current m0, m1 = 0v, 2.7v v in 5v 1 a m0, m1 = 0v, 2.7v v in 5v 2 a m0, m1 = 0v, 5v < v in 10v 25 a dv cc operating current m0, m1 = dv cc , c in = 1mhz 62 0 a dv cc shutdown current m0, m1 = 0v 1 a v cc output voltage 0 i vcc 10ma, 2.7v v in 10v 0 i vcc 20ma, 3v v in 10v m0, m1 = dv cc 4.75 5.00 5.25 v m0 = dv cc , m1 = 0 2.80 3.00 3.20 v m0 = 0, m1 = dv cc v in ?0.3 v in v v cc output ripple v in = 3.6v, i vcc = 10ma, v cc = 5v 75 mv p-p absolute m axi m u m ratings w ww u (note 1)v in , dv cc to gnd ..................................... 0.3v to 12v v cc to gnd ............................................... 0.3v to 12v digital inputs to gnd ................................ 0.3v to 12v ldo, clk, rst, i/o to gnd ........ 0.3v to (v cc + 0.3v) v cc , ldo short-circuit duration ..................... indefinite storage temperature range ................. 65 c to 150 c temperature range ltc1555c/ltc1556c .............................. 0 c to 70 c ltc1555i/ltc1556i ........................... 40 c to 85 c extended commercial operating temperature range (note 2) ............................................. 40 c to 85 c lead temperature (soldering, 10 sec).................. 300 c package/order i n for m atio n w u u consult factory for military grade parts. order part number ltc1556cgnltc1556ign order part number ltc1555cgnltc1555ign t jmax = 150 c, ja = 135 c/ w 1 2 3 4 5 6 7 8 top view gn package 16-lead plastic ssop 16 15 14 13 12 11 10 9 cin rin data ddrv dv cc ss m1 m0 clk rst i/o v cc v in c1 + c1 gnd 1 2 3 4 5 6 7 8 9 10 top view gn package 20-lead plastic ssop 20 19 18 17 16 15 14 13 12 11 cin rin data ddrv en fb dv cc ss m1 m0 clk rst i/o ldo v cc v in c1 + c1 gnd gnd t jmax = 150 c, ja = 95 c/ w electrical characteristics v in = 2.7v to 10v, dv cc = 1.8v to 5.5v, controller digital pins tied to dv cc , sim digital pins floating, en, fb pins tied to gnd (ltc1556), c1 = 0.1 f, c out = 10 f unless otherwise specified. downloaded from: http:///
3 ltc1555/ltc1556 v in = 2.7v to 10v, dv cc = 1.8v to 5.5v, controller digital pins tied to dv cc , sim digital pins floating, en, fb pins tied to gnd (ltc1556), c1 = 0.1 f, c out = 10 f unless otherwise specified. electrical characteristics over the 40 c to 85 c temperature range by design or correlation, but are not production tested.note 3: the data and i/o pull-down drivers must also sink current sourced by the internal pull-up resistors. parameter conditions min typ max units v cc short-circuit current v cc shorted to gnd 12.5 40 ma auxiliary ldo v out (v ldo ) en = high, v cc = 5v, fb = ldo, i ldo = 5ma (ltc1556) 4.00 4.3 4.55 v auxiliary switch resistance en = high, v cc = 5v, fb = gnd (ltc1556) 18 30 fb input resistance (ltc1556) 200 k charge pump f osc 500 650 800 khz controller inputs/outputs, dv cc = 3v input current (i ih , i il ) m0, m1, ss, rin, cin ? 1 a ddrv, en ? 5 a high level input current (i ih ) data ?0 20 a low level input current (i il ) data 1m a high input voltage threshold (v ih ) m0, m1, rin, cin, ddrv, en 0.7 dv cc v data dv cc ?0.6 v low input voltage threshold (v il ) m0, m1, rin, cin, ddrv, en 0.2 dv cc v data 0.4 v high level output voltage (v oh ) data source current = 20 a, i/o = v cc 0.7 dv cc v low level output voltage (v ol ) data sink current = 200 a, i/o = 0v (note 3) 0.4 v data pull-up resistance between data and dv cc 13 20 28 k data output rise/fall time data loaded with 30pf 1.3 2 s sim inputs/outputs, dv cc = 3v, v cc = 3v or 5v i/o high input voltage threshold (v ih )i ih(max) = 20 a 0.5 v cc 0.7 v cc v i/o low input voltage threshold (v il )i il(max) = 1ma 0.4 v high level output voltage (v oh ) i/o, source current = 20 a, data or ddrv = dv cc 0.8 v cc v rst, clk, source current = 20 a 0.9 v cc v low level output voltage (v ol ) i/o, sink current = 1ma, data or ddrv = 0v (note 3) 0.4 v rst, clk, sink current = 200 a 0.4 v i/o pull-up resistance between i/o and v cc 6.5 10 14 k sim timing parameters, dv cc = 3v, v cc = 5v clk rise/fall time clk loaded with 30pf 18 ns rst, i/o rise/fall time rst, i/o loaded with 30pf 1 s clk frequency clk loaded with 30pf 5 mhz v cc turn-on time ss = dv cc , c out = 10 f, i vcc = 0 1 ms ss = 0v, c out = 10 f, i vcc = 0 6 ms v cc discharge time to 1v i vcc = 0, v cc = 5v, c out = 10 f3 m s the denotes specifications which apply over the specified temperature range.note 1: absolute maximum ratings are those values beyond which the life of a device may be impaired.note 2: c grade device specifications are guaranteed over the 0 c to 70 c temperature range. in addition, c grade device specifications are assured downloaded from: http:///
4 ltc1555/ltc1556 typical perfor m a n ce characteristics uw v in input voltage (v) 2 operating current ( a) 80 100 10 1555/56 g01 6040 4 6 8 120 85 c 25 c ?0 c no external load operating currentvs input voltage v in input voltage (v) 2 v cc output voltage (v) 5.0 5.1 10 1555/56 g03 4.94.8 4 6 8 5.2 i vcc = 10ma m0 = dv cc m1 = dv cc c out = 10 f t a = 25 c v in input voltage (v) 2 shutdown current ( a) 10 15 10 1555/56 g02 50 4 6 8 85 c ?0 c 20 25 c shutdown currentvs input voltage v cc output voltage vs input voltage (5v mode) v cc output voltage vs input voltage (3v mode) v in input voltage (v) 2 v cc output voltage (v) 3.0 3.1 10 1555/56 g04 2.92.8 4 6 8 3.2 i vcc = 10ma m0 = dv cc m1 = 0v c out = 10 f t a = 25 c 1v/div 1ms/div 1555/56 g05 v in = 3v ss = 0v 1v/div 1ms/div v in = 3v ss = dv cc 1555/56 g06 v cc output voltage turn-on time, ss enabled v cc output voltage turn-on time, ss disabled 5v v cc efficiency vs input voltage v in input voltage (v) 2 efficiency (%) 100 80 60 40 20 10 1555/56 g08 4 6 8 12 v cc = 5v i vcc = 10ma t a = 25 c 3v v cc efficiency vs input voltage v in input voltage (v) 0 efficiency (%) 100 80 60 40 20 8 1555/56 g07 2 4 6 10 v cc = 3v i vcc = 10ma t a = 25 c downloaded from: http:///
5 ltc1555/ltc1556 ltc1555/ltc1556cin (pin 1): clock input pin from controller. rin (pin 2): reset input pin from controller. data (pin 3): controller side data input/output pin. can be used for single pin bidirectional data transfer betweenthe controller and the sim card as long as the controller data pin is open drain. the controller output must be able to sink 1ma max when driving the data pin low due to the internal pull-up resistors on the data and i/o pins. if the controller data output is not open drain, then the ddrv pin should be used for sending data to the sim card and the data pin used for receiving data from the sim card (see figure 1). ddrv (pin 4): optional data input pin for sending data to the sim card. when not needed, the ddrv pin shouldbe left floating or tied to dv cc (an internal 1 a current source will pull the ddrv pin up to dv cc if left floating). dv cc (pins 5/7): supply voltage for controller side digital i/o pins. may be between 1.8v and 5.5v (typically 3v) . ss (pins 6/8): soft start enable pin. a logic low will enable the charge pump inrush current limiting feature.a logic high will disable the soft start feature and allow v cc to be ramped as quickly as possible upon start-up and coming out of shutdown.m1 (pins 7/9): mode control bit 1 (see truth table). m0 (pins 8/10): mode control bit 0 (see truth table). this table defines the various operating modes that maybe obtained via the m0 and m1 mode control pins. truth table m0 m1 mode 0v 0v shutdown (v cc = 0v) 0v dv cc v cc = v in dv cc 0v v cc = 3v dv cc dv cc v cc = 5v gnd (pins 9/11, 12): ground for both the sim and the controller. should be connected to the sim gnd contactas well as to the v in /controller gnd. proper grounding and supply bypassing is required to meet 10kv esdspecifications. c1 (pins 10/12): charge pump flying capacitor nega- tive input.c1 + (pins 11/13): charge pump flying capacitor positive input.v in (pins 12/14): charge pump input voltage pin. input voltage range is 2.7v to 10v. connect a 10 f low esr input bypass capacitor close to the v in pin. v cc (pins 13/15): sim card v cc output. this pin should be connected to the sim v cc contact. the v cc output voltage is determined by the m0 and m1 pins (see truthtable). v cc is discharged to gnd during shutdown (m0, m1 = 0v). a 10 f low esr output capacitor should connect close to the v cc pin. i/o (pins 14/18): sim side i/o pin. the pin is an open drain output with a nominal pull-up resistance of 10k andshould be connected to the sim i/o contact. the sim card must sink up to 1ma max when driving the i/o pin low due to the internal pull-up resistors on the i/o and data pins. the i/o pin is held active low when the part is in shutdown. rst (pins 15/19): level shifted reset output pin. should be connected to the sim rst contact.clk (pins 16/20): level shifted clock output pin. should be connected to the sim clk contact. careful tracerouting is recommended due to fast rise and fall edge speeds. pi n fu n ctio n s uuu downloaded from: http:///
6 ltc1555/ltc1556 pi n fu n ctio n s uuu ltc1556 only en (pin 5): auxiliary ldo/power switch enable pin. a logic high on this pin from the controller will enable theauxiliary ldo output. when the ldo is disabled, the ldo output will float or be pulled to ground by the load. if left floating, the en pin will be pulled down to gnd by an internal 1 a current source. fb (pin 6): auxiliary ldo feedback pin. when fb is connected to the ldo pin (pin 17), the ldo output isregulated to 4.3v (typ). if the fb pin is left open or tied to block diagra m w ground, the regulator acts as a 30 switch between v cc and ldo.ldo (pin 17): ldo output pin. this pin should be tied to the fb pin for 4.3v ldo operation. the 4.3v ldo outputis usable only when v cc is 5v (or greater). it is not available when v cc = 3v. the ldo output may also be used as a 30 power switch if the fb pin is grounded or left floating. when used as a regulator, ldo must bebypassed to gnd with a 3.3 f capacitor. the ldo output current will subtract from available v cc current. 1.23v 61k 153k fb en 1555/56 bd ddrv optional 1 a 1 a ldo i/o frequency synthesizer power ltc1555/ltc1556 ltc1556 only 4.3v + data 20k 10k clk cin rst dv cc ss 3v rin gnd m0 m1 v in v batt c in 10 f v cc i/o clk rstgnd v cc c1 + 0.1 f c1 gnd step-up/ step-down charge pump dc/dc converter sim controller v cc c out 10 f c ldo 10 f + + downloaded from: http:///
7 ltc1555/ltc1556 the ltc1555/ltc1556 perform the two primary func-tions necessary for 3v controllers (e.g., gsm cellular telephone controllers, smart card readers, etc.) to com- municate with 5v sims or smart cards. they produce a regulated 5v v cc supply for the sim and provide level translators for communication between the sim and thecontroller. v cc voltage regulator the regulator section of the ltc1555/ltc1556 (refer tothe block diagram) consists of a step-up/step-down charge pump dc/dc converter. the charge pump can operate over a wide input voltage range (2.7v to 10v) while maintaining a regulated v cc output. the wide v in range enables the parts to be powered directly from a battery (ifdesired) rather than from a 3v dc/dc converter output. when v in is less than the desired v cc the parts operate as switched capacitor voltage doublers. when v in is greater than v cc the parts operate as gated switch step-down converters. in either case, voltage conversion requiresonly one small flying capacitor and output capacitor. the v cc output can be programmed to either 5v or 3v via the m0 and m1 mode pins. this feature is useful inapplications where either a 5v or 3v sim may be used. the charge pump v cc output may also be connected directly to v in if desired. when the charge pump is put into shutdown (m0, m1 = 0), v cc is pulled to gnd via an internal switch to aid in proper system supply sequencing.the soft start feature limits inrush currents upon start-up or coming out of shutdown mode. when the ss pin is tied to gnd, the soft start feature is enabled. this limits the ef- fective inrush current out of v in to approximately 25ma (c out = 10 f). inrush current limiting is especially useful when powering the ltc1555/ltc1556 from a 3v dc/dcoutput since the unlimited inrush current may approach 200ma and cause voltage transients on the 3v supply. how- ever, in cases where fast turn-on time is desired, the soft start feature may be overridden by tying the ss pin to dv cc . applicatio n s i n for m atio n wu u u capacitor selectionfor best performance, it is recommended that low esr (< 0.5 ) capacitors be used for both c in and c out to reduce noise and ripple. the c in and c out capacitors should be either ceramic or tantalum and should be 10 f or greater (ceramic capacitors will produce the smallest output ripple). if the input source impedance is very low (< 0.5 ), c in may not be needed. increasing the size of c out to 22 f or greater will reduce output voltage ripple?articularly with high v in voltages (8v or greater). a ceramic capacitor is recom-mended for the flying capacitor c1 with a value of 0.1 f or 0.22 f. output ripplenormal ltc1555/ltc1556 operation produces voltage ripple on the v cc pin. output voltage ripple is required for the parts to regulate. low frequency ripple exists due tothe hysteresis in the sense comparator and propagation delays in the charge pump enable/disable circuits. high frequency ripple is also present mainly from the esr (equivalent series resistance) in the output capacitor. typical output ripple (v in < 8v) under maximum load is 75mv peak-to-peak with a low esr, 10 f output capaci- tor. for applications requiring v in to exceed 8v, a 22 f or larger c out capacitor is recommended to maintain maxi- mum ripple in the 75mv range.the magnitude of the ripple voltage depends on several factors. high input voltages increase the output ripple since more charge is delivered to c out per charging cycle. a large c1 flying capacitor (> 0.22 f) also increases ripple in step-up mode for the same reason. large output currentload and/or a small output capacitor (< 10 f) results in higher ripple due to higher output voltage dv/dt. high esrcapacitors (esr > 0.5 ) on the output pin cause high frequency voltage spikes on v out with every clock cycle. a 10 f ceramic capacitor on the v cc pin should produce acceptable levels of output voltage ripple in nearly allapplications. however, there are several ways to further downloaded from: http:///
8 ltc1555/ltc1556 applicatio n s i n for m atio n wu u u reduce the ripple. a larger c out capacitor (22 f or greater) will reduce both the low and high frequency ripple due tothe lower c out charging and discharging dv/dt and the lower esr typically found with higher value (larger casesize) capacitors. a low esr ceramic output capacitor will minimize the high frequency ripple, but will not reduce the low frequency ripple unless a high capacitance value is chosen (10 f or greater). a reasonable compromise is to use a 10 f to 22 f tantalum capacitor in parallel with a 1 f to 3.3 f ceramic capacitor on v out to reduce both the low and high frequency ripple. an rc filter may also be usedto reduce high frequency voltage spikes (see figure 1). hundred milliseconds to completely shut down. to ensureprompt and proper v cc shutdown, always force the m0 and m1 pins to a logic low state before shutting down thedv cc supply (see figure 2). similarly, bring the dv cc supply to a valid level before allowing the m0 and m1 pinsto go high when coming out of shutdown. this can be achieved with pull-down resistors from m0 and m1 to gnd if necessary. (note: shutting down the dv cc supply with v in active is not recommended with early date code material. consult factory for valid date code starting pointfor shutting down the dv cc supply.) level translatorsall sims and smart cards contain a clock input, reset input and a bidirectional data input/output. the ltc1555/ ltc1556 provide level translators to allow controllers to communicate with the sim (see figures 3a and 3b). the clk and rst inputs to the sim are level shifted from the controller supply rails (dv cc and gnd) to the sim supply rails (v cc and gnd). the data input to the sim may be provided two different ways. the first method is to use thedata pin as a bidirectional level translator. this configu- ration is only allowed if the controller data output pin is open drain (all sim i/o pins are open drain). internal pull- up resistors are provided for both the data pin and the figure 3b. level translator connections forone-directional controller side data flow cin rin data ddrv dv cc clk rst i/o v cc clk to sim rst to sim data from sim data to sim ltc1555/ltc1556 controller side sim side 1555/56 f3b figure 3a. level translator connections forbidirectional controller data pin cin rin data ddrv dv cc clk rst i/o v cc clk to sim rst to sim data to/from sim ltc1555/ltc1556 controller side sim side 1555/56 f3a figure 2. recommended dv cc shutdown and start-up timing m0 dv cc 0v m1 dv cc 0v dv cc dv cc 0v v cc v cc 0v 1555/56 f02 shutting down the dv cc supply to conserve power, the dv cc supply may be shut down while the v in supply is still active. when the dv cc supply is brought to 0v, weak internal currents will force theltc1555/ltc1556 into shutdown mode regardless of the voltages present on the m0 and m1 pins. however, if the m0 and m1 pins are floating or left connected to dv cc as the supply is shut down, the parts may take several figure 1. v cc output ripple reduction techniques 15 f tantalum lt1555/56 f01 v cc sim v cc sim v cc 1 f ceramic 10 f v cc 10 f 2 ltc1555/ ltc1556 + downloaded from: http:///
9 ltc1555/ltc1556 i/o pin on the sim side. the second method is to use theddrv pin to send data to the sim and use the data pin to receive data from the sim. when the ddrv pin is not used, it should either be left floating or tied to dv cc . level translation with dv cc > v cc it is assumed that most applications for these parts willuse controller supply voltages (dv cc ) less than or equal to v cc . in cases where dv cc is greater than v cc by more than 0.6v or so, the parts?operation will be affected in thefollowing ways: 1) a small dc current (up to 100 a) will flow from dv cc to v cc through the data pull-up resistor, n-channel pass device and the i/o pull-up resistor(except when the part is in shutdown at which time dv cc is disconnected from v cc by turning off the pass device). if the v cc load current is less than the dv cc current, the v cc output may be pulled out of regulation until sufficient load current pulls v cc back into regulation. 2) when the sim is sending data back to the controller, a logic high onthe i/o pin will result in the data pin being pulled up to [v cc + 1/3(dv cc ?v cc )], not all the way up to dv cc . for example, if dv cc is 5v and v cc is 3v, the data pin will only swing from 0.1v to 3.67v when receiving data from the sim side. optional ldo outputthe ltc1556 also contains an internal ldo regulator for providing a low noise boosted supply voltage for low power external circuitry (e.g., frequency synthesizers, etc.) tying the fb pin to the ldo pin provides a regulated 4.3v at the ldo output (see figure 4). a 3.3 f (minimum) capacitor is applicatio n s i n for m atio n wu u u required to ensure output stability. a 10 f low esr capaci- tor is recommended, however, to minimize ldo outputnoise. the ldo output may also be used as an auxiliary switch to v cc . if the fb pin is left floating or is tied to gnd, the ldo pin will be internally connected to the v cc output through the p-channel pass device. the ldo may be dis-abled at any time by switching the en pin from dv cc to gnd. the 4.3v ldo output is usable only when v cc is 5v (or greater). it is not available when v cc = 3v. figure 4. auxiliary ldo connections (ltc1556 only) v ref 61k v cc = 5v 1 a ldo off on 10 f tant 4.3v 1555/56 f04 i ldo 0ma to 10ma fb 153k en + + 10kv esd protectionall pins that connect to the sim (clk, rst, i/o, v cc , gnd) withstand over 10kv of human body model (100pf/1.5k ) esd. in order to ensure proper esd protection, carefulboard layout is required. the gnd pins should be tied directly to a gnd plane. the v cc capacitor should be located very close to the v cc pin and tied immediately to the gnd plane. downloaded from: http:///
10 ltc1555/ltc1556 package descriptio n u dimensions in inches (millimeters) unless otherwise noted. gn package 16-lead plastic ssop (narrow 0.150) (ltc dwg # 05-08-1641) gn16 (ssop) 1197 * dimension does not include mold flash. mold flash shall not exceed 0.006" (0.152mm) per side ** dimension does not include interlead flash. interlead flash shall not exceed 0.010" (0.254mm) per side 12 3 4 5 6 7 8 0.229 ?0.244 (5.817 ?6.198) 0.150 ?0.157** (3.810 ?3.988) 16 15 14 13 0.189 ?0.196* (4.801 ?4.978) 12 11 10 9 0.016 ?0.050 (0.406 ?1.270) 0.015 0.004 (0.38 0.10) 45 0 ?8 typ 0.007 ?0.0098 (0.178 ?0.249) 0.053 ?0.068 (1.351 ?1.727) 0.008 ?0.012 (0.203 ?0.305) 0.004 ?0.0098 (0.102 ?0.249) 0.025 (0.635) bsc downloaded from: http:///
11 ltc1555/ltc1556 package descriptio n u dimensions in inches (millimeters) unless otherwise noted. gn package 20-lead plastic ssop (narrow 0.150) (ltc dwg # 05-08-1641) 0.337 ?0.344* (8.560 ?8.737) gn20 (ssop) 1197 * dimension does not include mold flash. mold flash shall not exceed 0.006" (0.152mm) per side ** dimension does not include interlead flash. interlead flash shall not exceed 0.010" (0.254mm) per side 12 3 4 5 6 7 8910 0.229 ?0.244 (5.817 ?6.198) 0.150 ?0.157** (3.810 ?3.988) 16 17 18 19 20 15 14 13 12 11 0.016 ?0.050 (0.406 ?1.270) 0.015 0.004 (0.38 0.10) 45 0 ?8 typ 0.007 ?0.0098 (0.178 ?0.249) 0.053 ?0.068 (1.351 ?1.727) 0.008 ?0.012 (0.203 ?0.305) 0.004 ?0.0098 (0.102 ?0.249) 0.025 (0.635) bsc information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no represen-tation that the interconnection of its circuits as described herein will not infringe on existing patent rights. downloaded from: http:///
12 ltc1555/ltc1556 15556f lt/tp 0398 4k ? printed in usa ? linear technology corporation 1997 linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax: (408) 434-0507 telex: 499-3977 www.linear-tech.com related parts part number description comments ltc1514-3.3/ltc1514-5 regulated step-up/step-down charge pumps with low bat comparator 3.3v and 5v output versions ltc1515 series regulated step-up/step-down charge pumps with reset output adjustable, 3v/5v, 3.3v/5v versions ltc1516 micropower, regulated 5v charge pump dc/dc converter i out = 20ma (v in 2v), i out = 50ma (v in 3v) ltc1517-5 micropower, regulated 5v charge pump dc/dc converter ltc1522 without shutdown and packaged in sot-23 ltc1522 micropower, regulated 5v charge pump dc/dc converter i out = 20ma (v in 3v), i q = 6 a ltc1550-4.1 low noise, charge pump voltage inverter 1mv p-p ripple at 900khz ltc660 100ma charge pump dc/dc converter 5v to 5v at 100ma 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 cin rin data ddrv en fb dv cc ss m1 m0 clk rst i/o v cc 5v 5% i vcc 10ma clk rst i/o ldo v cc v in c1 + c1 gnd gnd 0.1 f 10 f ltc1556 3v gsm controller sim v in 2.7v to 10v 3v 10 f 1555/56 ta02 v cc gnd + 10 f 4.3v 50ma auxiliary ldo/power switch (frequency synthesizer) + typical applicatio n u sim interface with auxilary power downloaded from: http:///

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